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Nov 24, 2024
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ECNG 661/6211 - Nanoscale CMOS (3 cr.)
Description
The increasing complexity of nanoscale CMOS technology imposes important constraints on the design of analog integrated circuits: while circuit performance using downscaled CMOS is largely improved in terms of speed, other analog figures of merit, such as transistor gain, are degraded. Reduced voltage headroom often requires the adoption of ultra-low-voltage techniques particularly in moderate inversion. Furthermore, variability is an important bottleneck impairing design in scaled technologies. The course covers issues ranging from technology and compact modeling aspects, to analog circuit design retargeting and methodologies for variability reduction using digital tuning, and optimization aspects on the system level.
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