ECNG 000/5219 - High-Performance Integrated Circuit Modeling (3 cr.)

 

Description
Nano-meter CMOS devices (short channel effects, velocity saturation, device leakage, thermal effects, degradation effects NBTI, etc), Dynamic, short-circuit, and leakage power consumption of CMOS circuits, low power design, Classic I/O Modeling and design, The interconnect bottle-neck (modeling and analysis), Noise in integrated circuits, Approximate temporal information in RC and RLC trees (Elmore, Wyatt, Penfield-Rubinstien delay models, and equivalent Elmore delay for RLC trees), Model order reduction (AWE, PRIMA, numerical issues, stability, etc),3-D Modeling, Thermal effects in integrated circuits, Power distribution network models, electromigration, Ldi/dt noise, and RI drops, High-speed clock distribution network issues: Retiming, register allocation, skew control, and clock scheduling.

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